vishay siliconix dg2517, dg2518 document number: 74333 s-82589-rev. b, 27-oct-08 www.vishay.com 1 3- , high bandwidth, dual spdt analog switch features ? 1.8 v to 5.5 v single supply operation ?low r on : 3 at 4.2 v ? 242 mhz, - 3 db bandwidth ? low off-isolation, - 51 db at 10 mhz ? + 1.6 v logic compatible benefits ? high linearity ? low power consumption ? high bandwidth ? full rail signal swing range applications ? usb/uart signal switching ? audio/video switching ? cellular phone ? media players ? modems ? hard drives ? pcmcia description the dg2517, dg2518 are low-voltage dual single-pole/ double-throw monolithic cmos analog switches. designed to operate from 1.8 v to 5. 5 v power supply, the dg2517, dg2518 achieves a bandwidth of 242 mhz while providing low on-resistance (3 ), excellent on-re sistance matching (0.2 ) and flatness (1 ) over the entire signal range. the dg2517, dg2518 offers t he advantage of high linearity that reduces signal distortion, making ideal for audio, video, and usb signal routing applications. additionally, the dg2517, dg2518 are 1.6 v logic compatible within the full operation voltage range. built on vishay siliconix?s proprietary sub-micron high- density process, the dg2517, dg2518 brings low power consumption at the same time as reduces pcb spacing with the msop10 and dfn10 packages. as a committed partner to the community and the environment, vishay siliconix manufactures this product with the lead (pb)-free dev ice terminations. the dfn package has a nickel-palladium-gold device termination and is represented by the lead (pb)-free "-e4" suffix. the msop package uses 100 % matte tin device termination and is represented by the lead (pb)- free "-e3" suffix. both the matte tin and nickel-palladium-gold device terminations meet all jedec standards for reflow and msl ratings. functional block diagram and pin configuration com1 nc1 v+ 1 2 3 10 9 top view in1 no1 gnd 8 dg2517 nc2 com2 4 5 7 no2 in2 6 com1 no1 v+ 1 2 3 10 9 top view in1 nc1 gnd 8 dg2518 no2 com2 4 5 7 nc2 in2 6 truth table logic nc1 and nc2 no1 and no2 0onoff 1offon ordering information temp. range package part number - 40 c to 85 c msop-10 dg2517dq-t1-e3 dg2518dq-t1-e3 dfn-10 DG2517DN-T1-E4 dg2518dn-t1-e4 rohs compliant
www.vishay.com 2 document number: 74333 s-82589-rev. b, 27-oct-08 vishay siliconix dg2517, dg2518 notes: a. signals on nc, no, or com or in exceeding v+ will be clamped by inte rnal diodes. limit forward diode current to maximum curr ent ratings. b. all leads welded or soldered to pc board. c. derate 4.0 mw/c above 70 c. d. derate 14.9 mw/c above 70 c. notes: a. room = 25 c, full = as determined by the operating suffix. b. typical values are for design aid only, not guaranteed nor subject to production testing. c. the algebraic convention whereby the most negative value is a minimum and the most po sitive a maximum, is used in this data sheet. d. guarantee by design, nor s ubjected to production test. e. v in = input voltage to perform proper function. f. guaranteed by 5 v leakage testing, not production tested. absolute maximum ratings parameter limit unit reference to gnd v+ - 0.3 to + 6 v in, com, nc, no a - 0.3 to (v+ + 0.3) continuous current (any terminal) 50 ma peak current (pulsed at 1 ms, 10 % duty cycle) 200 storage temperature (d suffix) - 65 to 150 c power dissipation (packages) b msop-10 c 320 mw dfn-10 d 1191 specifications (v+ = 3 v) parameter symbol test conditions otherwise unless specified v+ = 3 v, 10 %, v in = 0.5 or 1.4 v e temp. a limits - 40 c to 85 c unit min. b typ. c max. b analog switch analog signal range d v no , v nc , v com full 0 v+ v on-resistance r on v+ = 2.7 v, v com = 1.5 v i no/nc = 10 ma room full 3.2 4.5 5.0 r on flatness r on flatness v+ = 2.7 v, v com = 1.5, 2 v i no/nc = 10 ma room full 1.0 1.4 16 r on match between channels r on v+ = 2.7 v, v com = 1.5 v i no/nc = 10 ma room full 0.1 0.3 0.4 switch off leakage current f i no(off), i nc(off) v+ = 3.6 v, v no , v nc = 0.3 v/ 3 v v com = 3 v/0.3 v room full - 1 - 10 1 10 na i com(off) room full - 1 - 10 1 10 channel-on leakage current f i com(on) v+ = 3.6 v, v no, v nc = v com = 0.3 v/3 v room full - 1 - 10 1 10 digital control input high voltage d v inh full 1.4 v input low voltage v inl full 0.5 input capacitance c in full 4 pf input current i inl or i inh full 1 1 a dynamic characteristics tu r n - o n t i m e t on v+ = 2.7 v, v no or v nc = 1.5 v r l = 300 , c l = 35 pf room full 15 30 50 ns turn-off time t off room full 10 25 35 break-before-make time t d v no or v nc = 1.5 v, r l = 300 , c l = 35 pf full 1 charge injection d q inj c l = 1 nf, v gen = 1.5 v, r gen = 0 room 1 pc - 3 db bandwidth bw 0 dbm, c l = 5 pf, r l = 50 room 242 mhz off-isolation d oirr r l = 50 , c l = 5 pf f = 1 mhz room - 71 db f = 10 mhz room - 51 crosstalk d x ta l k r l = 50 , c l = 5 pf f = 1 mhz room - 73 f = 10 mhz room - 55 n o , n c off capacitance d c no(off) v in = 0 or v+, f = 1 mhz room 8 pf c nc(off) room 8 channel-on capacitance d c no(on) room 35 c nc(on) room 35 power supply power supply current i+ v in = 0 or v+ full 0.01 1.0 a
document number: 74333 s-82589-rev. b, 27-oct-08 www.vishay.com 3 vishay siliconix dg2517, dg2518 notes: a. room = 25 c, full = as determined by the operating suffix. b. typical values are for design aid only, not guaranteed nor subject to production testing. c. the algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. d. guarantee by design, nor subjected to production test. e. v in = input voltage to perform proper function. f. guaranteed by 5 v leakage testing, not production tested. stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indi cated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended per iods may affect device reliability. specifications (v+ = 5 v) parameter symbol test conditions otherwise unless specified v+ = 5 v, 10 %, v in = 0.8 or 2.0 v e temp. a limits - 40 c to 85 c unit min. b typ. c max. b analog switch analog signal range d v no , v nc , v com full 0 v+ v on-resistance r on v+ = 4.2 v, v com = 3.5 v, i no/nc = 10 ma room full 34.0 4.3 r on flatness r on flatness v+ = 4.2 v, v com = 1, 2, 3.5 v i no/nc = 10 ma room full 1.1 1.4 1.6 r on match between channels r on v+ = 4.2 v, v com = 3.5 v, i no/nc = 10 ma room full 0.1 0.3 0.4 switch off leakage current i no(off), i nc(off) v+ = 5.5 v v no , v nc = 1 v/4.5 v, v com = 4.5 v/1 v room full - 1 - 10 1 10 na i com(off) room full - 1 - 10 1 10 channel-on leakage current i com(on) v+ = 5.5 v, v com = v no , v nc = 1 v/4.5 v room full - 1 - 10 1 10 digital control input high voltage d v inh full 2.0 v input low voltage v inl full 0.8 input capacitance c in full 4 pf input current i inl or i inh v in = 0 v or v+ full 1 1 a dynamic characteristics tu r n - o n t i m e t on v+ = 4.2 v, v no or v nc = 3 v r l = 300 , c l = 35 pf room full 12 25 45 ns turn-off time t off room full 820 30 break-before-make time t d v no or v nc = 3 v, r l = 300 , c l = 35 pf full 1 charge injection d q inj c l = 1 nf, v gen = 2.5 v, r gen = 0 room 2 pc - 3 db bandwidth bw 0 dbm, c l = 5 pf, r l = 50 room 242 mhz off-isolation d oirr r l = 50 , c l = 5 pf f = 1 mhz room - 71 db f = 10 mhz room - 51 crosstalk d x ta l k r l = 50 , c l = 5 pf f = 1 mhz room - 73 f = 10 mhz room - 55 source-off capacitance d c no(off) v in = 0 or v+, f = 1 mhz room 8 pf c nc(off) room 8 channel-on capacitance d c no(on) room 35 c nc(on) room 35 power supply power supply range v+ 1.8 5.5 v power supply current i+ v in = 0 or v+ full 0.01 1.0 a
www.vishay.com 4 document number: 74333 s-82589-rev. b, 27-oct-08 vishay siliconix dg2517, dg2518 typical characteristics 25 c, unless otherwise noted r on vs. v com and supply voltage supply current vs. temperature leakage current vs. temperature 012345 v com - analog v oltage ( v ) 0 1 2 3 4 5 6 7 8 9 10 v + = 2.7 v v + = 4.2 v v + = 1. 8 v t = 25 c i n o/ n c = 10 ma ( ) e c n a t s i s e r - n o - r n o - 60 - 40 - 20 0 20 40 60 8 0 100 1 1000 10 000 temperat u re (c) v + = 5 v v i n = 0 v 10 100 ) a p ( t n e r r u c y l p p u s - + i - 40 - 15 10 35 60 85 1 1000 temperature (c) 10 100 ) a p ( t n e r r u c e g a k a e l i no(off) , i nc(off) i com(off) i com(on) r on vs. analog voltage and temperature supply current vs. input switching frequency leakage vs. analog voltage 0 1 2 3 4 5 012345 25 c v com - analog v oltage ( v ) 25 c ( ) e c n a t s i s e r - n o - r n o v + = 2.7 v - 40 c v + = 4.2 v - 40 c 8 5 c 8 5 c 10 10k 100k 10m 10 ma 1 ma 10 a 1 a 10 na input switching frequency (hz) ) a ( t n e r r u c y l p p u s - + i 1 na 100 na 100 a v+ = 5.5 v 100 1k 1m - 80 - 60 - 40 - 20 0 20 40 60 80 0.0 1.0 2.0 3.0 4.0 5.0 v com , v no , v nc - analog voltage (v) ) a p ( t n e r r u c e g a k a e l v+ = 5.5 v i nc(off) , i no(off) i com(off) i com(on)
document number: 74333 s-82589-rev. b, 27-oct-08 www.vishay.com 5 vishay siliconix dg2517, dg2518 typical characteristics 25 c, unless otherwise noted switching time vs. temperature off-isolation and crosstalk vs. frequency - 60 - 40 - 20 0 20 40 60 8 0 100 r l = 300 / t n o ( s) e m i t g n i h c t i w s - t f f o temperat u re (c) 0 2 4 6 8 10 12 14 16 1 8 t off , v + = 2.7 v t o n , v + = 4.2 v t o n , v + = 2.7 v t off , v + = 4.2 v 100k 10m 100m 1g 1m freq u ency (hz) ) b d ( x , r r i o k l a t - 90 - 8 0 - 70 - 60 - 50 - 40 - 30 - 20 - 10 0 oirr v + = 5 v r l = 50 x talk insertion loss vs. frequency charge injection vs. analog voltage 100k 10m 100m 1g 1m freq u ency (hz) loss (db) - 12 - 10 - 8 - 6 - 4 - 2 0 v + = 5 v r l = 50 - 80 - 60 - 40 - 20 0 20 40 012345 v com - analog voltage (v) ) c p ( n o i t c e j n i e g r a h c q - v+ = 5 v v+ = 3 v switching threshold vs. supply voltage v + - s u pply v oltage ( v ) r h t g n i h c t i w s -) v ( d l o h s e v t 0 0.5 1 1.5 2 2.5 1.5 2 2.5 3 3.5 4 4.5 5
www.vishay.com 6 document number: 74333 s-82589-rev. b, 27-oct-08 vishay siliconix dg2517, dg2518 test circuits figure 1. switching time switch input c l (includes fixture and stray capacitance) v+ in no or nc c l 35 pf com logic input r l 300 v out gnd v+ 50 % 0 v logic input switch output t on t off logic ?1? = switch on logic input waveforms inverted for switches that have the opposite logic sense. 0 v switch output v out v com r l r l r on 0.9 x v out t r < 5 ns t f < 5 ns v inh v inl figure 2. break-before-make interval c l (includes fixture and stray capacitance) nc v no no v nc 0 v logic input switch output v o v nc = v no t r < 5 ns t f < 5 ns 90 % t d t d in com v+ gnd v+ c l 35 pf v o r l 300 v inl v inh figure 3. charge injection off on on in v out v out q = v out x c l c l = 1 nf r gen v out com v in = 0 - v+ in v gen gnd v+ v+ in depends on switch configuration: input polarity determined by sense of switch. + nc or no
document number: 74333 s-82589-rev. b, 27-oct-08 www.vishay.com 7 vishay siliconix dg2517, dg2518 test circuits vishay siliconix maintains worldwide manufacturing capability. pr oducts may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?74333 . figure 4. off-isolation in gnd nc or no 0 v, 2.0 v 10 nf com off isolation = 20 log v com v no nc r l analyzer v+ v+ com figure 5. channel off/on capacitance nc or no f = 1 mhz in com gnd 0 v, 2.0 v meter hp4192a impedance analyzer or equivalent 10 nf v+ v+
notes: 1. die thickness allowable is 0.203 0.0127. 2. dimensioning and tolerances per ansi.y14.5m-1994. 3. dimensions ?d? and ?e 1 ? do not include mold flash or protrusions, and are measured at datum plane -h- , mold flash or protrusions shall not exceed 0.15 mm per side. 4. dimension is the length of terminal for soldering to a substrate. 5. terminal positions are shown for reference only. 6. formed leads shall be planar with respect to one another within 0.10 mm at seating plane. 7. the lead width dimension does not include dambar protrusion. allowable dambar protrusion shall be 0.08 mm total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the lead foot. minimum space between protrusions and an adjacent lead to be 0.14 mm. see detail ?b? and section ?c-c?. 8. section ?c-c? to be determined at 0.10 mm to 0.25 mm from the lead tip. 9. controlling dimension: millimeters. 10. this part is compliant with jedec registration mo-187, variation aa and ba. 11. datums -a- and -b- to be determined datum plane -h- . 12. exposed pad area in bottom side is the same as teh leadframe pad size. 5 n n-1 a b c 0.20 (n/2) tips) 2x n/2 2 1 0.60 0.50 0.60 e top view e see detail ?b? -h- 3 d -a- seating plane a 1 a 6 c 0.10 side view 0.25 bsc 4 l -c- seating plane 0.07 r. min 2 places parting line detail ?a? (scale: 30/1) 0.48 max detail ?b? (scale: 30/1) dambar protrusion 7 c 0.08 m b s a s b b 1 with plating base metal c 1 c section ?c-c? scale: 100/1 (see note 8) see detail ?a? a 2 0.05 s c c ? 3 e 1 -b- end view e1 0.95 package information vishay siliconix document number: 71245 12-jul-02 www.vishay.com 1 msop: 10?leads jedec part number: mo-187, (variation aa and ba) n = 10l millimeters dim min nom max note a - - 1.10 a 1 0.05 0.10 0.15 a 2 0.75 0.85 0.95 b 0.17 - 0.27 8 b 1 0.17 0.20 0.23 8 c 0.13 - 0.23 c 1 0.13 0.15 0.18 d 3.00 bsc 3 e 4.90 bsc e 1 2.90 3.00 3.10 3 e 0.50 bsc e 1 2.00 bsc l 0.40 0.55 0.70 4 n 10 5 0 4 6 ecn: t-02080?rev. c, 15-jul-02 dwg: 5867
bottom view notes: 1. all dimensions are in millimeters and inches. 2. n is the total number of terminals. 3. dimension b applies to metallized terminal and is measured between 0.15 and 0.30 mm from terminal tip. 4. coplanarity applies to the exposed heat sink slug as well as the terminal. 5. the pin #1 identifier may be either a mold or marked feature, it must be located within the zone iindicated. e/2 5 index area d/2 e/2 5 c 0.15 2x c 0.15 2x package information vishay siliconix document number: 73181 29-nov-04 www.vishay.com 1 dfn-10 lead (3 x 3) millimeters inches dim min nom max min nom max a 0.80 0.90 1.00 0.031 0.035 0.039 a1 0.00 0.02 0.05 0.000 0.001 0.002 a3 0.20 bsc 0.008 bsc b 0.18 0.23 0.30 0.007 0.009 0.012 d 3.00 bsc 0.118 bsc d2 2.20 2.38 2.48 0.087 0.094 0.098 e 3.00 bsc 0.118 bsc e2 1.49 1.64 1.74 0.059 0.065 0.069 e 0.50 bsc 0.020 bsc l 0.30 0.40 0.50 0.012 0.016 0.020 *use millimeters as the primary measurement. ecn: s-42134?rev. a, 29-nov-04 dwg: 5943
legal disclaimer notice www.vishay.com vishay revision: 02-oct-12 1 document number: 91000 disclaimer all product, product specifications and data are subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employee s, and all persons acting on it s or their behalf (collectivel y, vishay), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, repres entation or guarantee regarding the suitabilit y of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicable law, vi shay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation specia l, consequential or incidental damages, and (iii) any and all i mplied warranties, including warra nties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of products for certain type s of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in generic applications. such statements are not binding statements about the suitability of products for a particular application. it is the customers responsib ility to validate that a particu lar product with the properties descri bed in the product specification is suitable fo r use in a particular application. parameters provided in datasheets and/or specification s may vary in different applications an d performance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vish ays terms and condit ions of purchase, including but not limited to the warranty expressed therein. except as expressly indicate d in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vi shay product could result in personal injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk. pleas e contact authorized vishay personnel to ob tain written terms and conditions regarding products designed for such applications. no license, express or implied, by estoppel or otherwise, to any intellectual prope rty rights is granted by this document or by any conduct of vishay. product names and markings noted herein may be trad emarks of their respective owners. material category policy vishay intertechnology, inc. hereby certi fies that all its products that are id entified as rohs-compliant fulfill the definitions and restrictions defined under directive 2011/65/eu of the euro pean parliament and of the council of june 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment (eee) - recast, unless otherwis e specified as non-compliant. please note that some vishay documentation may still make reference to rohs directive 2002/95/ ec. we confirm that all the products identified as being compliant to directive 2002 /95/ec conform to directive 2011/65/eu. vishay intertechnology, inc. hereby certifi es that all its products that are identified as ha logen-free follow halogen-free requirements as per jedec js709a stan dards. please note that some vishay documentation may still make reference to the iec 61249-2-21 definition. we co nfirm that all the products identified as being compliant to iec 61249-2-21 conform to jedec js709a standards.
|
